1. Field of the Invention
The invention relates in general to a polysilicon read only memory (ROM) and method of fabrication thereof, and more particularly to a 3D polysilicon ROM and method of fabrication thereof.
2. Description of the Related Art
3D memories can be much lower cost than conventional 2D memories. If a conventional memory occupies A square millimeters of silicon area, then a 3D memory comprising N planes of bits occupies approximately (A/N) square millimeters of silicon area. Reduced area means that more finished memory devices can be built on a single wafer, thereby reducing cost. Thus there is a strong incentive to pursue 3D memories having many planes of memory cells.
FIG. 1 is a cross-sectional view showing a conventional 3D polysilicon ROM. Referring first to FIG. 1, which is a cross-sectional vies along the direction of bit lines, a conventional 3D polysilicon read only memory (ROM) 10 is a multilayer structure and includes at least: a silicon substrate 110, an isolated silicon dioxide (SiO2) layer 111, a N-Type heavily doped (N+) polysilicon layer 120, a dielectric layer 130, a P-Type lightly doped (P−) polysilicon layers 140, a oxide layer 124.
The isolated SiO2 layer 111 is deposited on the silicon substrate 110, and the N-Type heavily doped (N+) polysilicon layer 120 is deposited on the isolated SiO2 layer 111. The N+ polysilicon layer 120 is further defined a plurality of parallel, separate word lines (WL), such as word lines 122a, 122b, 122c in FIG. 1. The oxide layer 124 is filled in the space between the word lines 122a, 122b, 122c. The dielectric layer 130 is deposited on the word lines 122a, 122b, 122c and on the oxide layer 124.
The P-Type lightly doped (P−) polysilicon layer 140 is deposited on the dielectric layer 130 and further defines a plurality of parallel, separate bit lines (BL). The bit lines overlap the word lines 122a, 122b, 122c, from a top view, to form a shape approximating a cross.
However, the antifuse breakdown voltage is high between two polysilicon layers in the conventional 3D polysilicon ROM. And, the asymmetrical structure would result in different programming voltage, on current for sense amplifier. In general, the oxide breakdown voltage is high, so it's a key issue to reduce programming voltage. Moreover, the antifuse breakdown is hard to define if the antifuse material is uniform and rough. The antifuse breakdown region is hard to define, so the programming voltages are difficult to be controlled. Hence, the yield in array architectures is low.